• Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logic • Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage • Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure • Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues • Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems